PyTorch: Fused MoE Kernels and Native Reductions
Activity clusters around single-kernel fusion for Mixture-of-Experts GLU blocks and native ahead-of-time coverage for CUDA reductions, plus Intel backend consolidation and Inductor hot-path trims.
Duration: PT2M33S
Episode overview
This episode is a short developer briefing from PyTorch.
It explains recent repository work in plain language.
- Show: PyTorch
- Published: 2026-10-17T13:00:29Z
- Audio duration: PT2M33S
Transcript excerpt
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Good morning, it's October 17th, 2026, and this is your PyTorch briefing.
The big signal is fusion — pushing more model logic into single high-performance kernels, for both Mixture-of-Experts blocks and core reductions.
First, CUDA reductions are going native ahead-of-time. A large stack from one contributor declares coverage for sum, mean, product, max, min, and index reductions like arg max and arg min. PR 20-12-12 expands dtype support to 64-bit float, integers, boolean, 8-bit float and complex, while PR 20-12-13 completes…
Second, Flex GEMM is closing the loop on Gated Linear Units. PR 20-11-99 adds chunked G-L-U epilogue outputs, building on work to read and write interleaved two-lane tensors and compose output transforms with captures and auxiliary outputs. The payoff is a Mixture-of-Experts backward — gate, up-projection, and…
Third, platform cleanup and compile hygiene. Intel is porting convolution forward, backward, and inner-product ops from I-deep into A-ten, led by PR 20-12-29 and PR 20-12-24, line-for-line with no behavior change — lower maintenance risk. On the compiler side, Inductor PRs 20-12-39, 20-12-37 and 20-12-32 cut device…
Also notable: a new 8-bit floating…
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